The present invention relates to the field of digital electronic circuits. More specifically, in one embodiment the invention provides an improved programmable logic device with enhanced output routing as well as associated methods of operation.
Programmable logic devices (PLDs) are well known to those in the electronics art. Such programmable logic devices are commonly referred to as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), EPLDs (Electronically Programmable Logic Devices), EEPLDs, LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to configure or program an off the shelf device for a specific application. Such devices include, for example, the well known Classic.TM. EPLDs, MAX.RTM. 5000 EPLDs, and FLEX.RTM. EPLDs all made by Altera.RTM..
These devices, while similar in some aspects of overall functionality, may be of very different types in terms of circuit architecture. One family of PLDs uses a sum-of-products (SOP) architecture whereby each output is the ORed sum of a number of ANDed product terms of the inputs. This family is represented by the Altera MAX.RTM. and Classic.TM. 5000 EPLDs. Another family of PLDs uses look-up tables (LUTs) to perform logic functions. This family is represented by the Altera FLEX.RTM. EPLDs.
Modern PLDs generally are constructed from small functional units variously referred to as logic modules or macrocells and herein referred to as logic elements (LEs). These LEs are typically identical or nearly identical throughout the PLD and perform a function that is a sub unit of the function of the entire PLD. For example, in a PLD based on an LUT architecture, the LEs might each be four input/one output LUTs. PLDs generally include an interconnect structure of conductors to provide a mechanism for selectively connecting the inputs and outputs of the LEs in order to perform the PLD functionality.
Larger PLD's of both the SOP and LUT type generally group the smaller LEs into larger functional units herein referred to as logic array blocks (LABs). The LABs can contain within them a local LAB interconnect that allows signals in one LE to be selectively connected to signals in a different LE in the same LAB and that transmits signals from the global interconnect to the inputs of the individual LEs. The LABs may be connected to one another and to input and output circuits by means of the global interconnect,
While such devices have met with substantial success, such devices also meet with certain limitations.
For example, larger PLDs are generally provided with a large number of external input/output pins for transmitting signals off-chip, but the interconnect structure of such PLDs is such that a particular LE on the chip has direct access to a very limited number of I/O pins. A typical PLD may have as many as two hundred to four hundred or more I/O pins. Such devices are also provided with an intricate global interconnect structure for allowing individual functional elements on the PLD to communicate signals with all other elements on the PLD. For reasons of conserving chip area, this global interconnect structure is connected to the external pins in a limited way such that a particular LE on the chip has direct access to a very limited number of I/O pins. If a signal from a LE must be transmitted to an I/O pin to which that LE does not have direct access, the signal must be routed through an additional LE that has direct access to that I/O pin. This can create problems in PLD reprogrammability and modifiability of certain logic designs. For example, if a minor modification in an application requires that a logic signal be routed to a different I/O pin, ideally the PLD should be easily reprogrammable to accommodate this modification. However, with the limitations of some prior art PLDs, rerouting a logic signal to a different I/O pin could require use of additional LEs. If these LEs were unavailable because they were being used in other parts of the design, modification of the chip to reroute the output signal might be impossible.
From the above it is seen that an improved programmable logic device is desired.